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UPI-C42 UPI-L42 UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER
Y
Y
Y Y Y Y
Pin Software and Architecturally Compatible with all UPI-41 and UPI-42 Products Low Voltage Operation with the UPIL42 Full 3 3V Support Hardware A20 Gate Support Suspend Power Down Mode Security Bit Code Protection Support 8-Bit CPU plus ROM OTP EPROM RAM I O Timer Counter and Clock in a Single Package 4096 x 8 ROM OTP 256 x 8 RAM 8-Bit Timer Counter 18 Programmable I O Pins DMA Interrupt or Polled Operation Supported
Y
Y
Y
Y Y Y Y
Y
Y
One 8-Bit Status and Two Data Registers for Asynchronous Slave-toMaster Interface Fully Compatible with all Intel and Most Other Microprocessor Families Interchangeable ROM and OTP EPROM Versions Expandable I O Sync Mode Available Over 90 Instructions 70% Single Byte Quick Pulse Programming Algorithm Fast OTP Programming Available in 40-Lead Plastic 44-Lead Plastic Leaded Chip Carrier and 44-Lead Quad Flat Pack Packages
(See Packaging Spec Order and S) 240800 Package Type P N
Y
The UPI-C42 is an enhanced CHMOS version of the industry standard Intel UPI-42 family It is fabricated on Intel's CHMOS III-E process The UPI-C42 is pin software and architecturally compatible with the NMOS UPI family The UPI-C42 has all of the same features of the NMOS family plus a larger user programmable memory array (4K) hardware A20 gate support and lower power consumption inherent to a CHMOS product The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low voltage 3 3V operation The UPI-C42 is essentially a ``slave'' microcontroller or a microcontroller with a slave interface included on the chip Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS Modules and iAPX family as well as other 8- 16- and 32-bit systems To allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM (OTP)
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Figure 1 DIP Pin Configuration
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Figure 2 PLCC Pin Configuration
Figure 3 QFP Pin Configuration
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1996
December 1995
Order Number 290414-003
UPI-C42 UPI-L42
Table 1 Pin Description
Symbol TEST 0 TEST 1 DIP Pin No 1 39 PLCC Pin No 2 43 QFP Pin No 18 16 Type I Name and Function TEST INPUTS Input pins which can be directly tested using conditional branch instructions FREQUENCY REFERENCE TEST 1 (T1) functions as the event timer input (under software control) TEST 0 (T0) is a multi-function pin used during PROM programming and ROM EPROM verification during Sync Mode to reset the instruction state to S1 and synchronize the internal clock to PH1 XTAL 1 XTAL 2 RESET 2 3 4 3 4 5 19 20 22 O I I OUTPUT Output from the oscillator amplifier INPUT Input to the oscillator amplifier and internal clock generator circuits RESET Input used to reset status flip-flops set the program counter to zero and force the UPI-C42 from the suspend power down mode RESET is also used during EPROM programming and verification SS 5 6 23 I SINGLE STEP Single step input used in conjunction with the SYNC output to step the program through each instruction (EPROM) This should be tied to a 5V when not used This pin is also used to put the device in Sync Mode by applying 12 5V to it CHIP SELECT Chip select input used to select one UPI microcomputer out of several connected to a common data bus EXTERNAL ACCESS External access input which allows emulation testing and ROM EPROM verification This pin should be tied low if unused READ I O read input which enables the master CPU to read data and status words from the OUTPUT DATA BUS BUFFER or status register COMMAND DATA SELECT Address Input used by the master processor to indicate whether byte transfer is data (A0 e 0 F1 is reset) or command (A0 e 1 F1 is set) A0 e 0 during program and verify operations WRITE I O write input which enables the master CPU to write data and command words to the UPI INPUT DATA BUS BUFFER OUTPUT CLOCK Output signal which occurs once per UPI instruction cycle SYNC can be used as a strobe for external circuitry it is also used to synchronize single step operation DATA BUS Three-state bidirectional DATA BUS BUFFER lines used to interface the UPI microcomputer to an 8-bit master system data bus PORT 1 8-bit PORT 1 quasi-bidirectional I O lines P10 -P17 access the signature row and security bit
CS EA
6 7
7 8
24 25
I I
RD A0
8 9
9 10
26 27
I I
WR SYNC
10 11
11 13
28 29
I O
D0 - D7 (BUS) P10 - P17
12- 19 27- 34
14- 21 30- 33 35- 38
30- 37 2 - 10
IO IO
2
UPI-C42 UPI-L42
Table 1 Pin Description (Continued)
Symbol P20 - P27 DIP Pin No 21- 24 35- 38 PLCC Pin No 24- 27 39- 42 QFP Pin No 39- 42 11 13- 15 Type IO Name and Function PORT 2 8-bit PORT 2 quasi-bidirectional I O lines The lower 4 bits (P20 -P23) interface directly to the 8243 I O expander device and contain address and data information during PORT 4 - 7 access P21 can be programmed to provide hardware A20 gate support The upper 4 bits (P24 -P27) can be programmed to provide interrupt Request and DMA Handshake capability Software control can configure P24 as Output Buffer Full (OBF) interrupt P25 as Input Buffer Full (IBF) interrupt P26 as DMA Request (DRQ) and P27 as DMA ACKnowledge (DACK) PROGRAM Multifunction pin used as the program pulse input during PROM programming During I O expander access the PROG pin acts as an address data strobe to the 8243 This pin should be tied high if unused POWER a 5V main power supply pin POWER a 5V during normal operation a 12 75V during programming operation Low power standby supply pin GROUND Circuit ground potential
PROG
25
28
43
IO
VCC VDD VSS
40 26 20
44 29 22
17 1 38
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Figure 4 Block Diagram
3
UPI-C42 UPI-L42
UPI-C42 L42 PRODUCT SELECTION GUIDE
UPI-C42 Low power CHMOS version of the UPI-42
Device 80C42 82C42PC 82C42PD 82C42PE 87C42 Package N PS NPS NPS NPS NPS 4K ROM 4K OTP ROM Device Phoenix MultiKey 42 firmware PS 2 style mouse support Phoenix MultiKey 42L firmware KBC and SCC for portable apps Phoenix MultiKey 42G firmware Energy Efficient KBC solution One Time Programmable Version Comments
UPI-L42 The low voltage 3 3V version of the UPI-C42
Device 80L42 82L42PC 82L42PD 87L42 Package N PS NPS NPS NPS 4K ROM 4K OTP ROM Device Phoenix MultiKey 42 firmware PS 2 style mouse support Phoenix MultiKey 42L firmware KBC and SCC for portable apps One Time Programmable Version Comments
N e 44 lead PLCC P e 40 lead PDIP S e 44 lead QFP D e 40 lead CERDIP KBC e Key Board Control SCC e Scan Code Control
THE INTEL 82C42
As shown in the UPI-C42 product matrix the UPIC42 is offered as a pre-programmed 80C42 with various versions of MultiKey 42 keyboard controller firmware developed by Phoenix Technologies Ltd
The 82C42PC provides a low powered solution for industry standard keyboard and PS 2 style mouse control The 82C42PD provides a cost effective means for keyboard and scan code control for notebook platforms The 82C42PE allows a quick time to market low cost solution for energy efficient desktop designs
4
UPI-C42 UPI-L42
4 P24 and P25 are port pins or Buffer Flag pins which can be used to interrupt a master processor These pins default to port pins on Reset If the ``EN FLAGS'' instruction has been executed P24 becomes the OBF (Output Buffer Full) pin A ``1'' written to P24 enables the OBF pin (the pin outputs the OBF Status Bit) A ``0'' written to P24 disables the OBF pin (the pin remains low) This pin can be used to indicate that valid data is available from the UPI (in Output Data Bus Buffer) If ``EN FLAGS'' has been executed P25 becomes the IBF (Input Buffer Full) pin A ``1'' written to P25 enables the IBF pin (the pin outputs the inverse of the IBF Status Bit A ``0'' written to P25 disables the IBF pin (the pin remains low) This pin can be used to indicate that the UPI is ready for data Data Bus Buffer Interrupt Capability
UPI-42 COMPATIBLE FEATURES
1 Two Data Bus Buffers one for input and one for output This allows a much cleaner Master Slave protocol
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2 8 Bits of Status ST7 ST6 ST5 ST4 F1 F0 IBF OBF D7 D6 D5 D4 D3 D2 D1 D0 ST4 -ST7 are user definable status bits These bits are defined by the ``MOV STS A'' single byte single cycle instruction Bits 4-7 of the acccumulator are moved to bits 4-7 of the status register Bits 0-3 of the status register are not affected
MOV STS A Op Code 90H
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1 D7
0
0
1
0
0
0
0 D0
EN FLAGS
Op Code 0F5H
1 D7
1
1
1
0
1
0
1 D0
3 RD and WR are edge triggered IBF OBF F1 and INT change internally after the trailing edge of RD or WR During the time that the host CPU is reading the status register the UPI is prevented from updating this register or is `locked out '
5 P26 and P27 are port pins or DMA handshake pins for use with a DMA controller These pins default to port pins on Reset If the ``EN DMA'' instruction has been executed P26 becomes the DRQ (DMA Request) pin A ``1'' written to P26 causes a DMA request (DRQ is activated) DRQ is deactivated by DACKRD DACKWR or execution of the ``EN DMA'' instruction
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DMA Handshake Capability
290414 - 8
5
UPI-C42 UPI-L42
If ``EN DMA'' has been executed P27 becomes the DACK (DMA ACKnowledge) pin This pin acts as a chip select input for the Data Bus Buffer registers during DMA transfers
EN DMA Op Code 0E5H
PROGRAM MEMORY BANK SWITCH
The switching of 2K program memory banks is accomplished by directly setting or resetting the most significant bit of the program counter (bit 11) see Figure 5 Bit 11 is not altered by normal incrementing of the program counter but is loaded with the contents of a special flip-flop each time a JMP or CALL instruction is executed This special flip-flop is set by executing an SEL PMB1 instruction and reset by SEL PMB0 Therefore the SEL PMB instruction may be executed at any time prior to the actual bank switch which occurs during the next branch instruction encountered Since all twelve bits of the program counter including bit 11 are stored in the stack when a Call is executed the user may jump to subroutines across the 2K boundary and the proper PC will be restored upon return However the bank switch flip-flop will not be altered on return
1
1
1
0
0
1
0
1
D7 D0 6 When EA is enabled on the UPI the program counter is placed on Port 1 and the lower four bits of Port 2 (MSB e P23 LSB e P10) On the UPI this information is multiplexed with PORT DATA (see port timing diagrams at end of this data sheet) 7 The UPI-C42 supports the Quick Pulse Programming Algorithm but can also be programmed with the Intelligent Programming Algorithm (See the Programming Section )
UPI-C42 FEATURES Programmable Memory Size Increase
The user programmable memory on the UPI-C42 will be increased from the 2K available in the NMOS product by 2X to 4K The larger user programmable memory array will allow the user to develop more complex peripheral control micro-code P2 3 (port 2 bit 3) has been designated as the extra address pin required to support the programming of the extra 2K of user programmable memory The new instruction SEL PMB1 (73h) allows for access to the upper 2K bank (locations 2048-4095) The additional memory is completely transparent to users not wishing to take advantage of the extra memory space No new commands are required to access the lower 2K bytes The SEL PMB0 (63h) has also been added to the UPI-C42 instruction set to allow for switching between memory banks
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Figure 5 Program Counter
INTERRUPT ROUTINES
Interrupts always vector the program counter to location 3 or 7 in the first 2K bank and bit 11 of the program counter is held at ``0'' during the interrupt service routine The end of the service routine is signaled by the execution of an RETR instruction Interrupt service routines should therefore be contained entirely in the lower 2K words of program memory The execution of a SEL PMB0 or SEL PMB1 instruction within an interrupt routine is not recommended since it will not alter PC11 while in the routine but will change the internal flip-flop
Extended Memory Program Addressing (Beyond 2K)
For programs of 2K words or less the UPI-C42 addresses program memory in the conventional manner Addresses beyond 2047 can be reached by executing a program memory bank switch instruction (SEL PMB0 SEL PMB1) followed by a branch instruction (JMP or CALL) The bank switch feature extends the range of branch instructions beyond their normal 2K range and at the same time prevents the user from inadvertently crossing the 2K boundary
Hardware A20 Gate Support
This feature has been provided to enhance the performance of the UPI-C42 when being used in a keyboard controller application The UPI-C42 design has included on chip logic to support a hardware GATEA20 feature which eliminates the need to provide firmware to process A20 command sequences
6
UPI-C42 UPI-L42
thereby providing additional user programmable memory space This feature is enabled by the A20EN instruction and remains enabled until the device is reset It is important to note that the execution of the A20EN instruction redefines Port 2 bit 1 as a pure output pin with read only characteristics The state of this pin can be modified only through a valid ``D1'' command sequence (see Table 1) Once enabled the A20 logic will process a ``D1'' command sequence (write to output port) by setting resetting the A20 bit on port 2 bit 1 (P2 1) without requiring service from the internal CPU The host can directly control the status of the A20 bit At no time during this host interface transaction will the IBF flag in the status register be activated Table 1 gives several possible GATEA20 command data sequences and UPI-C42 responses Table 1 D1 Command Sequences
A0 R W DB Pins IBF A20 1 0 1 1 0 1 1 1 0 1 1 1 0 W W W W W W W W W W W W W D1h DFh FFH(2) D1h DDh FFh D1h D1h DFh FFh D1h XXh(3) DDh 0 0 0 0 0 0 0 0 0 0 0 1 1 Comments
SUSPEND The execution of the suspend instruction (82h or E2h) causes the UPI-C42 to enter the suspend mode In this mode of operation the oscillator is not running and the internal CPU operation is stopped The UPI-C42 consumes s 40 mA in the suspend mode This mode can only be exited by RESET CPU operation will begin from PC e 000h when the UPI-C42 exits from the suspend power down mode
Suspend Mode Summary

Oscillator Not Running CPU Operation Stopped Ports Tristated with Weak ( E 2-10 mA) Pull-Up Micropower Mode (ICC s 40 mA) This mode is exited by RESET
n(1) Set A20 Sequence 1 Only DB1 Is Processed n n 0 n n n 1 n n n n Clear A20 Sequence
Double Trigger Set Sequence
Invalid Sequence No Change in State of A20 Bit
NOTES 1 Indicates that P2 1 remains at the previous logic level 2 Only FFh commands in a valid A20 sequence have no effect on IBF An FFh issued at any other time will activate IBF 3 Any command except D1
The above sequences assume that the GATEA20 logic has been enabled via the A20EN instruction As noted only the value on DB 1 (data bus bit 1) is processed This bit will be directly passed through to P2 1 (port 2 bit 1)
7
UPI-C42 UPI-L42
Table 2 covers all suspend mode pin states In addition to the suspend power down mode the UPI-C42 will also support the NMOS power down mode as outlined in Chapter 4 of the UPI-42AH users manual Table 2 Suspend Mode Pin States Pins Ports 1 and 2 Outputs Inputs DBB(1) Outputs Inputs System Control (RD WR CS A0) Reset Crystal Osc (XTAL1 XTAL2) Test 0 Test 1 Prog Sync EA SS ICC Suspend Tristate Weak Pull-Up Disabled Normal Normal Disabled
NEW UPI-C42 INSTRUCTIONS
The UPI-C42 will support several new instructions to allow for the use of new C42 features These instructions are not necessary to the user who does not wish to take advantage of any new C42 functionality The C42 will be completely compatible with all current NMOS code applications In order to use new features however some code modifications will be necessary All new instructions can easily be inserted into existing code by use of the ASM-48 macro facility as shown in the following example Macname MACRO DB 63H ENDM
New Instructions
Enabled Disabled Disabled High High Disabled No Pull-Up Disabled Weak Pull-Up
k 40 mA
The following is a list of additions to the UPI-42 instruction set These instructions apply only to the UPI-C42 These instructions must be added to existing code in order to use any new functionality SEL PMB0 Select Program Memory Bank 0 OPCODE 0110 0011 (63h)
PC Bit 11 is set to zero on next JMP or CALL instruction All references to program memory fall within the range of 0 - 2047 (0 - 7FFh) SEL PMB1 Select Program Memory Bank 1 OPCODE 0111 0011 (73h)
NOTES 1 DBB outputs are Tristate unless CS and RD are active DBB inputs are disabled unless CS and WR are active 2 A ``disabled'' input will not cause current to be drawn regardless of input level (within the supply range) 3 Weak pull-ups have current capability of typically 5 mA
PC Bit 11 is set to one on next JMP or CALL instruction All references to program memory fall within the range of 2048 - 4095 (800h - FFFh) ENA20 Enables Auto A20 hardware OPCODE 0011 0011 (33h)
Enables on chip logic to support Hardware A20 Gate feature Will remain enabled until device is reset
8
UPI-C42 UPI-L42
This circuitry gives the host direct control of port 2 bit 1 (P2 1) without intervention by the internal CPU When this opcode is executed P2 1 becomes a dedicated output pin The status of this pin is read-able but can only be altered through a valid ``D1'' command sequence (see Table 1) SUSPEND Invoke Suspend Power Down Mode OPCODE (E2h) 1000 0010 (82h) or 1110 0010
Pin XTAL 2 Reset Test 0 EA BUS P20-23 VDD PROG Clock Input
Function
Initialization and Address Latching Selection of Program or Verify Mode Activation of Program Verify Signature Row Security Bit Modes Address and Data Input Data Output During Verify Address Input Programming Power Supply Program Pulse Input
Enables device to enter micro power mode In this mode the external oscillator is off CPU operation is stopped and the Port pins are tristated This mode can only be exited via a RESET signal
PROGRAMMING AND VERIFYING THE UPI-C42
The UPI-C42 programming will differ from the NMOS device in three ways First the C42 will have a 4K user programmable array The UPI-C42 will also be programmed using the Intel Quick-Pulse Programming Algorithm Finally port 2 bit three (P2 3) will be used during program as the extra address pin required to program the upper 2K bank of additional memory None of these differences have any effect on the full CHMOS to NMOS device compatibility The extra memory is fully transparent to the user who does not need or want to use the extra memory space of the UPI-C42 In brief the programming process consists of activating the program mode applying an address latching the address applying data and applying a programming pulse Each word is programmed completely before moving on to the next and is followed by a verification step The following is a list of the pins used for programming and a description of their functions
WARNING An attempt to program a missocketed UPI-C42 will result in severe damage to the part An indication of a properly socketed part is the appearance of the SYNC clock output The lack of this clock may be used to disable the programmer
The Program Verify sequence is 1 Insert 87C42 in programming socket 2 CS e 5V VCC e 5V VDD e 5V RESET e 0V A0 e 0V TEST 0 e 5V clock applied or internal oscillator operating BUS floating PROG e 5V 3 TEST 0 e 0V (select program mode) 4 EA e 12 75V (active program mode) 5 VCC e 6 25V (programming supply) 6 VDD e 12 75V (programming power) 7 Address applied to BUS and P20-23 8 RESET e 5V (latch address) 9 Data applied to BUS 10 PROG e 5V followed by one 100 ms pulse to 0V 11 TEST 0 e 5V (verify mode) 12 Read and verify data on BUS 13 TEST 0 e 0V 14 RESET e 0V and repeat from step 6 15 Programmer should be at conditions of step 1 when the 87C42 is removed from socket Please follow the Quick-Pulse Programming flow chart for proper programming procedure shown in Figure 6
9
UPI-C42 UPI-L42
flow chart of the Quick-Pulse Programming Algorithm is shown in Figure 6 The entire sequence of program pulses and byte verifications is performed at VCC e 6 25V and VDD e 12 75V When programming has been completed all bytes should be compared to the original data with VCC e VDD e 5V A verify should be performed on the programmed bits to ensure that they have been correctly programmed The verify is performed with T0 e 5V VDD e 5V EA e 12 75V SS e 5V PROG e 5V A0 e 0V and CS e 5V In addition to the Quick-Pulse Programming Algorithm the UPI-C42 OPT is also compatible with Intel's Inteligent Programming Algorithm which is used to program the NMOS UPI-42AH OTP devices The entire sequence of program pulses and byte verifications is performed at VCC e 6 25V and VDD e 12 75V When the inteligent Programming cycle has been completed all bytes should be compared to the original data with VCC e 5 0 VDD e 5V
Verify
A verify should be performed on the programmed bits to determine that they have been correctly programmed The verify is performed with T0 e 5V VDD e 5V EA e 12 75V SS e 5V PROG e 5V A0 e 0V and CS e 5V
SECURITY BIT
The security bit is a single EPROM cell outside the EPROM array The user can program this bit with the appropriate access code and the normal programming procedure to inhibit any external access to the EPROM contents Thus the user's resident program is protected There is no direct external access to this bit However the security byte in the signature row has the same address and can be used to check indirectly whether the security bit has been programmed or not The security bit has no effect on the signature mode so the security byte can always be examined
290414 - 14
Figure 6 Quick-Pulse Programming Algorithm
Quick-Pulse Programming Algorithm
As previously stated the UPI-C42 will be programmed using the Quick-Pulse Programming Algorithm developed by Intel to substantially reduce the thorughput time in production programming The Quick-Pulse Programming Algorithm uses initial pulses of 100 ms followed by a byte verification to determine when the address byte has been successfully programmed Up to 25 100 ms pulses per byte are provided before a failure is recognized A
SECURITY BIT PROGRAMMING VERIFICATION Programming
a Read the security byte of the signature mode Make sure it is 00H
10
UPI-C42 UPI-L42
b Apply access code to appropriate inputs to put the device into security mode c Apply high voltage to EA and VDD pins d Follow the programming procedure as per the Quick-Pulse Programming Algorithm with known data on the databus Not only the security bit but also the security byte of the signature row is programmed e Verify that the security byte of the signature mode contains the same data as appeared on the data bus (If DB0-DB7 e high the security byte will contain FFH ) f Read two consecutive known bytes from the EPROM array and verify that the wrong data are retrieved in at least one verification If the EPROM can still be read the security bit may have not been fully programmed though the security byte in the signature mode has and will be present in the ROM and OTP versions Location 10H contains the manufacturer code For Intel it is 89H Location 11H contains the device code The code is 43H and 42H for the 8042AH 80C42 and OTP 8742AH 87C42 respectively The code is 44H for any device with the security bit set by Intel C User signature The user signature memory is implemented in the EPROM and consists of 2 bytes for the customer to program his own signature code (for identification purposes and quick sorting of previously programmed materials) D Test signature This memory is used to store testing information such as test data bin number etc (for use in quality and manufacturing control) E Security byte This byte is used to check whether the security bit has been programmed (see the security bit section) F UPI-C42 Intel Signature Applies only to CHMOS device Location 20H contains the manufacturer code and location 21H contains the device code The Intel UPI-C42 manufacturer's code is 99H The device ID's are 82H for the OTP version and 83H for the ROM version The device ID's are the same for the UPI-L42 The signature mode can be accessed by setting P10 e 0 P11 - P17 e 1 and then following the programming and or verification procedures The location of the various address partitions are as shown in Table 3
Verification
Since the security bit address overlaps the address of the security byte of the signature mode it can be used to check indirectly whether the security bit has been programmed or not Therefore the security bit verification is a mere read operation of the security byte of the signature row (0FFH e security bit programmed 00H e security bit unprogrammed) Note that during the security bit programming the reading of the security byte does not necessarily indicate that the security bit has been successfully programmed Thus it is recommended that two consecutive known bytes in the EPROM array be read and the wrong data should be read at least once because it is highly improbable that random data coincides with the correct ones twice
SYNC MODE
The Sync Mode is provided to ease the design of multiple controller circuits by allowing the designer to force the device into known phase and state time The Sync Mode may also be utilized by automatic test equipment (ATE) for quick easy and efficient synchronizing between the tester and the DUT (device under test) Sync Mode is enabled when SS pin is raised to high voltage level of a 12 volts To begin synchronization T0 is raised to 5 volts at least four clock cycles after SS T0 must be high for at least four X2 clock cycles to fully reset the prescaler and time state generators T0 may then be brought down during low state of X2 Two clock cycles later with the rising edge of X2 the device enters into Time State 1 Phase 1 SS is then brought down to 5 volts 4 clocks later after T0 RESET is allowed to go high 5 tCY (75 clocks) later for normal execution of code
SIGNATURE MODE
The UPI-C42 has an additional 64 bytes of EPROM available for Intel and user signatures and miscellaneous purposes The 64 bytes are partitioned as follows A Test code checksum This can accommodate up to 25 bytes of code for testing the internal nodes that are not testable by executing from the external memory The test code checksum is present on ROMs and OTPs B Intel signature This allows the programmer to read from the UPI-41AH 42AH C42 the manufacturer of the device and the exact product name It facilitates automatic device identification
11
UPI-C42 UPI-L42
Table 3 Signature Mode Table Address Test Code Checksum Intel Signature User Signature Test Signature Security Byte UPI-C42 Intel Signature User Defined UPI-C42 OTP EPROM Space 0 16H 10H 12H 14H 1FH 20H 22H or 0FH 1EH 11H 13H 15H 3FH 21H 3EH Device Type ROM OTP ROM OTP OTP ROM OTP ROM OTP ROM OTP ROM OTP No of Bytes 25 2 2 2 2 2 30
ACCESS CODE
The following table summarizes the access codes required to invoke the Sync Mode Signature Mode and the Security Bit respectively Also the programming and verification modes are included for comparison
Control Signals Modes T0 RST SS EA PROG VDD VCC 0 Programming Mode Verification Mode Sync Mode Signature Prog Mode Verify 0 0 0 1 STB High 0 0 0 1 Security Bit Byte Prog 0 0 Verify 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 1 HV 1 VDDH VCC 1 2 3 4 5 6 7 Data Bus Port 2 Access Code Port 1
0123 0 1 234567 Addr Addr Addr Addr a0 a1 X X X X X X a0 a1 X X X X X X
Address Data In Address Data Out X X X X X X
1 HV STB VDDH VCC 1 HV 1 HV HV 0 1 HV 1 1 X 1 VCC VCC VCC VCC VCC VCC X VDDH VCC
X XXX 000 000 000 000 000 000 000 000
X X XXXXXX 0 1 1 1 1XX1
Addr (see Sig Mode Table) Data In Addr (see Sig Mode Table) Data Out Address Data In Address Data Out
1 HV STB VDDH VCC 1 HV 1 HV 1 HV 1 1 1 VCC VCC VCC VCC VDDH VCC
1 HV STB VDDH VCC 1 HV 1 HV 1 1 VCC VCC VCC VCC
NOTE 1 a0 e 0 or 1 a1 e 0 or 1 a0 must e a1
12
UPI-C42 UPI-L42
SYNC MODE TIMING DIAGRAMS
290414 - 15
Minimum Specifications SYNC Operation Time tSYNC e 3 5 XTAL 2 Clock cycles Reset Time tRS e 4 tCY NOTE The rising and falling edges of T0 should occur during low state of XTAL 2 clock
APPLICATIONS
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Figure 7 UPI-C42 Keyboard Controller
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Figure 8 8088-UPI-C42 Interface
13
UPI-C42 UPI-L42
APPLICATIONS (Continued)
290414 - 10
Figure 9 8048H-UPI-C42 Interface
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Figure 10 UPI-C42-8243 Keyboard Scanner
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Figure 11 UPI-C42 80-Column Matrix Printer Interface
14
UPI-C42 UPI-L42
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground Power Dissipation 0 C to a 70 C
b 65 C to a 150 C b 0 5V to a 7V
NOTICE This is a production data sheet The specifications are subject to change without notice
15W
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
DC CHARACTERISTICS
Symbol VIL VIH VIH1 VOL VOL1 VOL2 VOH VOH1 IIL IOFL ILI Parameter Input Low Voltage
TA e 0 C to a 70 C VCC e VDD e a 5V g10% a 3 3V g10% UPI-L42 UPI-C42 Min
b0 5
UPI-L42 Min
b0 3
Max 08 VCC VCC 0 45 0 45 0 45
Max
a0 8
Units V V V V V V V All Pins
Notes
Input High Voltage (Except XTAL2 RESET) Input High Voltage (XTAL2 RESET) Output Low Voltage (D0 -D7) Output Low Voltage (P10P17 P20P27 Sync) Output Low Voltage (PROG) Output High Voltage (D0 -D7) Output High Voltage (All Other Outputs) Input Leakage Current (T0 T1 RD WR CS A0 EA) Output Leakage Current (D0 -D7 High Z State) Low Input Load Current (P10P17 P20P27) Low Input Load Current (RESET SS) Port Sink Current (P10P17 P20P27) VDD Supply Current
20 35
20 20
VCC a 0 3 VCC a 0 3 0 45 0 45 0 45
IOL e 2 0 mA UPI-C42 IOL e 1 3 mA UPI-L42 IOL e 1 6 mA UPI-C42 IOL e 1 mA UPI-L42 IOL e 1 0 mA UPI-C42 IOL e 0 7 mA UPI-L42 IOH e b 400 mA UPI-C42 IOH e b 260 mA UPI-L42 IOH e b 50 mA UPI-C42 IOH e b 25 mA UPI-L42
24 24
g10
24 24
g10
mA mA mA
VSS s VIN s VCC VSS a 0 45 s VOUT s VCC Port Pins Min VIN e 2 4V Max VIN e 0 45V VIN s VIL VCC e 3 0V VIH e 5 0V
g10
g10
b 50 b 250 b 35
b 175
ILI1 IHI IDD
b 40
b 40
mA
50 4 25
mA mA
15
UPI-C42 UPI-L42
DC CHARACTERISTICS
TA e 0 C to a 70 C VCC e VDD e a 5V g10% a 3 3V g10% UPI-L42 (Continued) Symbol ICC a IDD Parameter Total Supply Current Active Mode 12 5 MHz Suspend Mode IDD Standby IIH CIN CIO Power Down Supply Current Input Leakage Current (P10 -P17 P20 -P27) Input Capacitance I O Capacitance UPI-C42 Min Max 30 40 5 100 10 20 UPI-L42 Min Max 20 26 35 100 10 20 Units Notes
mA mA mA mA pF pF
Typical 14 mA UPI-C42 9 mA UPI-L42 Osc Off(1 4) NMOS Compatible Power Down Mode VIN e VCC TA e 25 C (1) TA e 25 C (1)
NOTE 1 Sampled not 100% tested
DC CHARACTERISTICS
Symbol VDDH VDDL VPH VPL VEAH VEAL IDD IEA
PROGRAMMING (UPI-C42 AND UPI-L42)
Parameter Min 12 5 4 75 20
b0 5
TA e 25 C g5 C VCC e 6 25V g0 25V VDD e 12 75V g0 25V Max 13 5 25 55 08 13 0 5 25 50 0 10 Units V(1) V V V V(2) V mA mA(4)
VDD Program Voltage High Level VDD Voltage Low Level PROG Program Voltage High Level PROG Voltage Low Level Input High Voltage for EA EA Voltage Low Level VDD High Voltage Supply Current EA High Voltage Supply Current
12 0
b0 5
NOTES 1 Voltages over 13V applied to pin VDD will permanently damage the device 2 VEAH must be applied to EA before VDDH and removed after VDDL 3 VCC must be applied simultaneously or before VDD and must be removed simultaneously or after VDD 4 Sampled not 100% tested
16
UPI-C42 UPI-L42
AC CHARACTERISTICS
TA e 0 C to a 70 C VSS e 0V VCC e VDD e a 5V g10% a 3 3V g10% for the UPI-L42
NOTE All AC Characteristics apply to both the UPI-C42 and UPI-L42
DBB READ Symbol tAR tRA tRR tAD tRD tDF DBB WRITE Symbol tAW tWA tWW tDW tWD Parameter CS A0 Setup to WRv CS A0 Hold After WRu WR Pulse Width Data Setup to WRu Data Hold After WRu Min 0 0 160 130 0 Max Units ns ns ns ns ns Parameter CS A0 Setup to RDv CS A0 Hold After RDu RD Pulse Width CS A0 to Data Out Delay RDv to Data Out Delay RDu to Data Float Delay 0 Min 0 0 160 130 130 85 Max Units ns ns ns ns ns ns
17
UPI-C42 UPI-L42
AC CHARACTERISTICS
TA e 0 C to a 70 C VSS e 0V VCC e VDD e a 5V g10% a 3 3V g10% for the UPI-L42 (Continued) CLOCK Symbol tCY UPI-C42 UPI-L42 tCYC UPI-C42 UPI-L42 tPWH tPWL tR tF
NOTE 1 tCY e 15 f(XTAL)
Parameter Cycle Time Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time
Min 12 80 30 30
Max 9 20 613
Units ms(1) ns ns ns
10 10
ns ns
AC CHARACTERISTICS
Symbol tACC tCAC tACD tCRQ
NOTE 1 CL e 150 pF
DMA Parameter Min 0 0 0 130 110 Max Units ns ns ns ns(1)
DACK to WR or RD RD or WR to DACK DACK to Data Valid RD or WR to DRQ Cleared
AC CHARACTERISTICS
Symbol tCP tPC tPR tPF tDP tPD tPP
PORT 2 Parameter f(tCY)(3) 1 15 tCY b 28 1 10 tCY 8 15 tCY b 16 0 2 10 tCY 1 10 tCY b 80 6 10 tCY 250 45 750 Min 55 125 650 150 Max Units ns(1) ns(2) ns(1) ns(2) ns(1) ns(2) ns
Port Control Setup Before Falling Edge of PROG Port Control Hold After Falling Edge of PROG PROG to Time P2 Input Must Be Valid Input Data Hold Time Output Data Setup Time Output Data Hold Time PROG Pulse Width
NOTES 1 CL e 80 pF 2 CL e 20 pF 3 tCY e 1 25 ms
18
UPI-C42 UPI-L42
AC CHARACTERISTICS
(87C42 87L42 ONLY) Symbol tAW tWA tDW tWD tPW tTW tWT tDO tWW tr tf tCY tRE tOPW tDE
PROGRAMMING (UPI-C42 AND UPI-L42)
TA e 25 C g5 C VCC e 6 25V g0 25V VDDL e a 5V g0 25V VDDH e 12 75V g0 25V
Parameter Address Setup Time to RESETu Address Hold Time after RESETu Data in Setup Time to PROGv Data in Hold Time after PROGu Initial Program Pulse Width Test 0 Setup Time for Program Mode Test 0 Hold Time after Program Mode Test 0 to Data Out Delay RESET Pulse Width to Latch Address PROG Rise and Fall Times CPU Operation Cycle Time RESET Setup Time before EAu Overprogram Pulse Width EA High to VDD High
Min 4tCY 4tCY 4tCY 4tCY 95 4tCY 4tCY
Max
Units
105
ms
4tCY 4tCY 05 25 4tCY 2 85 1tCY 78 75 ms(1) 100 3 75 ms ms
NOTES 1 This variation is a function of the iteration counter value X 2 If TEST 0 is high tDO can be triggered by RESETu
AC TESTING INPUT OUTPUT WAVEFORM
INPUT OUTPUT
AC TESTING LOAD CIRCUIT
290414 - 16 290414 - 17
19
UPI-C42 UPI-L42
DRIVING FROM AN EXTERNAL SOURCE
290414 - 18
290414 - 19
NOTE See XTAL1 Configuration Table
Rise and Fall Times Should Not Exceed 10 ns Resistors to VCC are Needed to Ensure VIH e 3 5V if TTL Circuitry is Used
LC OSCILLATOR MODE
CRYSTAL OSCILLATOR MODE
L C NOMINAL 45 H 20 pF 5 2 MHz 120 H 20 pF 3 2 MHz
fe
1 2q0LC C a 3Cpp 2 C1 C2 C3
Ce
Cpp j 5- 10 pF Pin-to-Pin Capacitance 290414 - 20 Each C Should be Approximately 20 pF including Stray Capacitance
290414 - 21 5 pF (STRAY 5 pF) (CRYSTAL a STRAY) 8 pF 20 - 30 pF INCLUDING STRAY
Crystal Series Resistance Should be Less Than 30X at 12 5 MHz
XTAL1 Configuration Table XTAL1 Connection 1) to Ground Not recommended for CHMOS designs Causes approximately 16 mA of additional current flow through the XTAL1 pin on UPIC42 and approximately 11 mA of additional current through XTAL1 on the UPI-L42 2) 10 KX Resistor to Ground Recommended configuration for designs which will use both NMOS and CHMOS parts This configuration limits the additional current through the XTAL1 pin to approximately 1 mA while maintaining compatibility with the NMOS device 3) Not Connected Low power configuration recommended for CHMOS only designs to provide lowest possible power consumption This configuration will not work with the NMOS device
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UPI-C42 UPI-L42
WAVEFORMS
READ OPERATION DATA BUS BUFFER REGISTER
290414 - 22
WRITE OPERATION
DATA BUS BUFFER REGISTER
290414 - 23
CLOCK TIMING
290414 - 24
21
UPI-C42 UPI-L42
WAVEFORMS (Continued)
COMBINATION PROGRAM VERIFY MODE
290414 - 25
NOTES 1 A0 must be held low (0V) during program verify modes 2 For VIH VIH1 VIL VIL1 VDDH and VDDL please consult the D C Characteristics Table 3 When programming the 87C42 a 0 1 mF capacitor is required across VDD and ground to suppress spurious voltage transients which can damage the device
VERIFY MODE
290414 - 26
NOTES 1 PROG must float if EA is low 2 PROG must float or e 5V when EA is high 3 P10 - P17 e 5V or must float 4 P24 - P27 e 5V or must float 5 A0 must be held low during programming verify modes
22
UPI-C42 UPI-L42
WAVEFORMS (Continued)
DMA
290414 - 27
PORT 2
290414 - 28
PORT TIMING DURING EXTERNAL ACCESS (EA)
290414 - 29
On the Rising Edge of SYNC and EA is Enabled Port Data is Valid and can be Strobed On the Trailing Edge of Sync the Program Counter Contents are Available
23
UPI-C42 UPI-L42
Table 4 UPI Instruction Set
Mnemonic Description Bytes 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 Cycles 1 1 2 1 1 MOV Rr 2 1 1 2 1 1 2 1 1 MOVP3 A 2 1 1 1 1 1 1 1 1 1 1 A MOV Rr data MOV A PSW MOV PSW A XCH A Rr XCH A XCHD A MOVP A Rr Rr A data Mnemonic DATA MOVES MOV A Rr MOV A Rr MOV A data MOV Rr A MOV Rr A Description Move register to A Move data memory to A Move immediate to A Move A to register Move A to data memory Move immediate to register Move immediate to data memory Move PSW to A Move A to PSW Exchange A and register Exchange A and data memory Exchange digit of A and register Move to A from current page Move to A from page 3 Bytes 1 1 2 1 1 2 2 1 1 1 1 1 1 1 Cycles 1 1 2 1 1 2 2 1 1 1 1 1 2 2 ACCUMULATOR ADD A Rr Add register to A Add data memory ADD A Rr to A Add immediate to A ADD A data ADDC A Rr Add register to A with carry Add data memory ADDC A Rr to A with carry ADDC A data Add immediate to A with carry ANL A Rr AND register to A AND data memory ANL A Rr to A ANL A data AND immediate to A ORL A Rr OR register to A OR data memory ORL A Rr to A OR immediate to A ORL A data XRL A Rr Exclusive OR register to A Exclusive OR data XRL A Rr memory to A Exclusive OR immeXRL A data diate to A INC A Increment A DEC A Decrement A CLR A Clear A CPL A Complement A DA A Decimal Adjust A SWAP A Swap nibbles of A RL A Rotate A left RLC A Rotate A left through carry RR A Rotate A right RRC A Rotate A right through carry INPUT OUTPUT IN A Pp Input port to A OUTL Pp A Output A to port ANL Pp data AND immediate to port ORL Pp data OR immediate to port IN A DBB Input DBB to A clear IBF OUT DBB A Output A to DBB set OBF MOV STS A A4 - A7 to Bits 4-7 of Status MOVD A Pp Input Expander port to A MOVD Pp A Output A to Expander port ANLD Pp A AND A to Expander port ORLD Pp A OR A to Expander port
TIMER COUNTER MOV A T Read Timer Counter MOV T A Load Timer Counter STRT T Start Timer STRT CNT Start Counter STOP TCNT Stop Timer Counter EN TCNTI Enable Timer Counter Interrupt DIS TCNTI Disable Timer Counter Interrupt CONTROL EN A20 EN DMA EN I DIS I EN FLAGS SEL PMB0 SEL PMB1 SEL RB0 SEL RB1 Enable A20 Logic Enable DMA Handshake Lines Enable IBF Interrupt Diable IBF Interrupt Enable Master Interrupts Select Program memory bank 0 Select Program memory bank 1 Select register bank 0 Select register bank 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
1 1 2 2 1 1 1 1 1 1 1
2 2 2 2 1 1 1 2 2 2 2
UPI-C42 UPI-L42 Only
24
UPI-C42 UPI-L42
Table 4 UPI Instruction Set (Continued)
Mnemonic Description Bytes 1 1 1 1 1 2 1 1 Cycles 2 1 1 1 1 2 2 2 Mnemonic BRANCH JMP addr JMPP A DJNZ Rr addr JC addr JNC addr JZ addr JNZ addr JT0 addr JNT0 addr JT1 addr JNT1 addr JF0 addr JF1 addr JTF addr JNIBF addr JOBF addr JBb addr Description Jump unconditional Jump indirect Decrement register and jump Jump on Carry e 1 Jump on Carry e 0 Jump on A Zero Jump on A not Zero Jump on T0 e 1 Jump on T0 e 0 Jump on T1 e 1 Jump on T1 e 0 Jump on F0 Flag e 1 Jump on F1 Flag e 1 Jump on Timer Flag e 1 Clear Flag Jump on IBF Flag e0 Jump on OBF Flag e1 Jump on Accumulafor Bit Bytes 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Cycles 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 CONTROL (Continued) SUSPEND Invoke Suspend Powerdown mode NOP No Operation REGISTERS INC Rr Increment register INC Rr Increment data memory DEC Rr Decrement register SUBROUTINE CALL addr Jump to subroutine RET Return RETR Return and restore status FLAGS CLR C CPL C CLR F0 CPL F0 CLR F1 CPL F1 Clear Carry Complement Carry Clear Flag 0 Complement Flag 0 Clear F1 Flag Complement F1 Flag
1 1 1 1 1 1
1 1 1 1 1 1
UPI-C42 UPI-L42 Only
REVISION SUMMARY
The following has been changed since Revision -003 1 Delete all references to standby power down mode The following has been changed since Revision -002 1 Added information on keyboard controller product family 2 Added IHI specification for the UPI-L42 The following has been changed since Revision -001 1 Added UPI-L42 references and specification
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